View MAX9179_276369.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-2752; Rev 0; 2/03
Quad LVDS Receiver with Hysteresis
General Description
The MAX9179 is a quad low-voltage differential signaling (LVDS) line receiver designed for applications requiring high data rates, low power dissipation, and noise immunity. The receiver accepts four LVDS input signals and translates them to 3.3V LVCMOS output levels at speeds up to 400Mbps. The receiver features built-in hysteresis, which improves noise immunity and prevents multiple switching on slow transitioning inputs. The device supports a wide 0.038V to 2.362V commonmode input voltage range, allowing for ground potential differences and common-mode noise between the driver and the receiver. A fail-safe circuit sets the output high when the input is open, undriven and shorted, or undriven and terminated. Common enable inputs control the highimpedance outputs. The MAX9179 has a flow-through pinout for easy PC board layout, and is pin compatible with the MAX9121 and the DS90LV048A with the additional features of high ESD tolerance and built-in hysteresis. The MAX9179 operates from a single 3.3V supply, and is specified for operation from -40C to +85C. The device is offered in 16-pin TSSOP and thin QFN packages. o Guaranteed 400Mbps Data Rate o 50mV (typ) Hysteresis o Overshoot/Undershoot Protection (-1.0V or VCC + 1.0V) on Enables o IEC61000-4-2 Level 4 ESD Tolerance o AC Specifications Guaranteed with |VID| = 100mV o Single 3.3V Supply o Fail-Safe Circuit o Flow-Through Pinout Simplifies PC Board Layout Reduces Crosstalk o Low-Power CMOS Design o Conforms to ANSI TIA/EIA-644 LVDS Standard o High-Impedance Inputs when Powered Off o Pin Compatible with the MAX9121 and the DS90LV048A o Small Thin QFN Package Available
Features
MAX9179
Applications
Laser Printers Digital Copiers Cell-Phone Base Stations Telecom Switching Equipment LCD Displays Network Switches/Routers Backplane Interconnect Clock Distribution
Ordering Information
PART MAX9179EUE MAX9179ETE* TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 16 TSSOP 16 Thin QFN-EP**
*Future product--contact factory for availability. **EP = Exposed paddle. Functional Diagram appears at end of data sheet.
Pin Configurations
TOP VIEW
IN1- 1 IN1+ 2 IN2+ 3 IN2- 4 IN3- 5 IN3+ 6 IN4+ 7 IN4- 8 16 EN IN2+ 1 15 OUT1 14 OUT2 IN2- 2 11 VCC 12 OUT2 IN1+ 16 IN115 EN 14 OUT1 13
MAX9179
IN3- 3 EXPOSED PAD IN3+ 4 5 IN4+ 6 IN47 EN 8 OUT4 9 OUT3 10 GND
MAX9179
13 VCC 12 GND 11 OUT3 10 OUT4 9 EN
THIN QFN (LEADS UNDER PACKAGE)
TSSOP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Quad LVDS Receiver with Hysteresis MAX9179
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.0V IN_+, IN_- to GND .................................................-0.3V to +4.0V EN, EN to GND ...........................................-1.4V to (VCC + 1.4V) OUT_ to GND .............................................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70C) 16-Pin TSSOP (derate 9.4mW/C above +70C) .........755mW 16-Pin Thin QFN (derate 16.9mW/C above +70C).............................................................1349mW Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (RD = 1.5k, CS = 100pF) (IN_+, IN_-) ................................................................16kV IEC61000-4-2 (RD = 330, CS = 150pF) (IN_+, IN_-) Contact Discharge .......................................................8kV Air-Gap Discharge .....................................................15kV Soldering Temperature (soldering, 10s) ..........................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, differential input voltage |VID| = 0.075V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25C.) (Notes 1, 2)
PARAMETER INPUTS (IN_+, IN_-) Differential Input High Threshold Differential Input Low Threshold Hysteresis Input Current Power-Off Input Current Fail-Safe Input Resistor 1 Fail-Safe Input Resistor 2 OUTPUTS (OUT_) Open, undriven short, or undriven parallel termination VID = +50mV Output Low Voltage Output Short-Circuit Current Output High-Impedance Current ENABLE INPUTS (EN, EN) Input High Voltage Input Low Voltage Input Current POWER SUPPLY Supply Current Disabled Supply Current ICC ICCZ Enabled, inputs open Disabled, inputs open 10.4 0.6 15 1.0 mA VIH VIL -1.0V EN, EN 0V IIN 0V EN, EN VCC VCC EN, EN VCC + 1.0V 2.0 -1.0 -1800 -20 -10 VCC + 1.0 +0.8 +10 +20 +1800 A V V VOL IOS IOZ IOL = 4.0mA, VID = -50mV Enabled, VID = +50mV, VOUT = 0 (Note 3) Disabled, VOUT = 0 or VCC -40 -1.0 0.1 -70 0.25 -120 +1.0 V mA A VCC 0.2 VCC 0.1 VTH VTL VTH - VTL IIN+, IINIOFF+, IOFFRIN1 RIN2 VCC = 0V VCC = 3.6V or 0V, Figure 2 VCC = 3.6V or 0V, Figure 2 Figure 1 Figure 1 Figure 1 -20 -20 40 280 -75 25 -25 50 +20 +20 65 455 75 mV mV mV A A k k SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage
VOH
IOH = -4.0mA
V
2
_______________________________________________________________________________________
Quad LVDS Receiver with Hysteresis
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, CL = 15pF, differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25C.) (Notes 4, 5, 6)
PARAMETER Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Pulse Skew | tPHLD - tPLHD | (Note 7) Differential Channel-to-Channel Skew, Same Part (Note 8) Differential Part-to-Part Skew (Note 9) Differential Part-to-Part Skew (Note 10) Rise Time Fall Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Maximum Operating Frequency SYMBOL tPHLD tPLHD Figures 3, 4 Figures 3, 4 |VID| = 0.1V to 0.15V tSKD1 |VID| = 0.15V to 0.2V |VID| = 0.2V to 1.2V |VID| = 0.1V to 0.15V tSKD2 |VID| = 0.15V to 0.2V |VID| = 0.2V to 1.2V tSKD3 tSKD4 tTLH tTHL tPHZ tPLZ tPZH tPZL fMAX RL = 2k, Figures 5, 6 (Note 11) RL = 2k, Figures 5, 6 (Note 11) RL = 2k, Figures 5, 6 (Note 11) RL = 2k, Figures 5, 6 (Note 11) All channels switching, CL = 15pF, VOL (max) = 0.25V, VOH (min) = VCC - 0.2V, 44% < duty cycle < 56% 200 0.77 0.74 10.6 11 4.8 4.8 250 120 80 CONDITIONS MIN 2.0 2.0 TYP 2.6 2.52 MAX 4.6 4.6 700 400 300 900 600 400 2.0 2.6 1.4 1.4 14 14 14 14 ns ns ns ns ns ns ns ns MHz ps ps UNITS ns ns
MAX9179
Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Parts are production tested at TA = +25C. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, and VID. Note 3: Short one output at a time. Note 4: AC parameters are guaranteed by design and characterization. Limits are set at 6 sigma. Note 5: CL includes scope probe and test jig capacitance. Note 6: Pulse generator differential output for all tests (unless otherwise noted): tR = tF < 1ns (0% to 100%), frequency = 100MHz, 50% duty cycle. Note 7: tSKD1 is the magnitude of the difference of the differential propagation delays in a channel. tSKD1 = | tPHLD - tPLHD |. Note 8: tSKD2 is the magnitude of the difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of the other channel on the same part. Note 9: tSKD3 is the magnitude of the difference of any differential propagation delays between parts at the same VCC and within 5C of each other. Note 10: tSKD4 is the magnitude of the difference of any differential propagation delays between parts operating over the rated supply and temperature ranges. Note 11: Pulse generator output for tPHZ, tPLZ, tPZH, and tPZL tests: tR = tF = 1.5ns (0.2VCC to 0.8VCC), 50% duty cycle, VOH = VCC + 1.0V settling to VCC, VOL = -1.0V settling to 0, frequency = 1MHz.
_______________________________________________________________________________________
3
Quad LVDS Receiver with Hysteresis MAX9179
Test Circuits/Timing Diagrams
VOUT VOH
IN_+ tPLHD 0.9VCC 0.5VCC tPHLD 0.9VCC 0.5VCC 0.1VCC IN_(0V DIFFERENTIAL) VID VCM = ((VIN_+) + (VIN_-))/2
VTL
VTH
OUT_
0.1VCC
tTLH
tTHL
-VID
VOL VID = 0 HYSTERESIS
Figure 4. Propagation Delay and Transition Time Waveforms
+VID
CL INCLUDES LOAD AND TEST JIG CAPACITANCE. S1 = VCC FOR tPZL AND tPLZ MEASUREMENTS. S1 = 0 FOR tPZH AND tPHZ MEASUREMENTS.
VCC
S1
Figure 1. Input Thresholds and Hysteresis
IN_+ IN_EN RL DEVICE UNDER TEST OUT_ CL
VCC RIN2
PULSE GENERATOR 50 EN
IN_+ RIN1
VCC - 0.3V OUT_
Figure 5. High-Impedance Delay Test Circuit
RIN1 IN_EN WHEN EN = LOW OR OPEN 1.5V 1.5V
VCC + 1.0V VCC
Figure 2. Fail-Safe Input Circuit
0 -1.0V VCC + 1.0V VCC EN WHEN EN = HIGH 1.5V 1.5V 0 -1.0V tPZL tPLZ 50% OUT_ WHEN VID = -75mV OUT_ WHEN VID = +75mV 0.5V tPHZ 0.5V 50% 0 tPZH VOL VOH VCC
IN_+ PULSE GENERATOR 50 IN_CL 50 OUT_
Figure 3. Propagation Delay and Transition Time Test Circuit 4
Figure 6. High-Impedance Delay Waveforms
_______________________________________________________________________________________
Quad LVDS Receiver with Hysteresis
Typical Operating Characteristics
(VCC = 3.3V, VCM = 1.2V, |VID| = 0.15V, CL = 15pF, f = 100MHz, TA = +25C, unless otherwise noted.)
MAX9179
SUPPLY CURRENT vs. FREQUENCY
MAX9179 toc01
SUPPLY CURRENT vs. TEMPERATURE
MAX9179 toc02
DC DIFFERENTIAL THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE
DC DIFFERENTIAL THRESHOLD VOLTAGE (mV) 30 20 10 0 -10 -20 -30 -40 3.0 3.1 3.2 3.3 VTL 3.4 3.5 3.6 VTH
MAX9179 toc03
110
16 14 SUPPLY CURRENT (mA) 12 10 8 6
40
90 SUPPLY CURRENT (mA)
70
50
30 ALL CHANNELS DRIVEN 10 0 50 100 150 200 250 300 350 FREQUENCY (MHz)
INPUTS OPEN 4 -40 -15 10 35 60 85 TEMPERATURE (C)
SUPPLY VOLTAGE (V)
OUTPUT SHORT-CIRCUIT CURRENT vs. SUPPLY VOLTAGE
MAX9179 toc04
OUTPUT HIGH VOLTAGE vs. SUPPLY VOLTAGE
DC INPUT (VID = +150mV) IOH = -4mA
MAX9179 toc05
-100 OUTPUT SHORT-CIRCUIT CURRENT (mA) DC INPUT (VID = +150mV) -80
3.6
OUTPUT HIGH VOLTAGE (V) 3.0 3.1 3.2 3.3 3.4 3.5 3.6
3.4
3.2
-60
3.0
-40
2.8 -20 SUPPLY VOLTAGE (V)
2.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
OUTPUT LOW VOLTAGE vs. SUPPLY VOLTAGE
DIFFERENTIAL PROPAGATION DELAY (ns) DC INPUT (VID = -150mV) IOL = 4mA
MAX9179 toc06
DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE
MAX9179 toc07
140
3.2 3.0 2.8 tPHLD 2.6 tPLHD 2.4 2.2 2.0
OUTPUT LOW VOLTAGE (mV)
130
120
110
100
90 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
5
Quad LVDS Receiver with Hysteresis MAX9179
Typical Operating Characteristics (continued)
(VCC = 3.3V, VCM = 1.2V, |VID| = 0.15V, CL = 15pF, f = 100MHz, TA = +25C, unless otherwise noted.)
DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE
MAX9179 toc08
DIFFERENTIAL PROPAGATION DELAY vs. COMMON-MODE VOLTAGE
MAX9179 toc09
DIFFERENTIAL PROPAGATION DELAY vs. DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9179 toc10
3.4 DIFFERENTIAL PROPAGATION DELAY (ns) 3.2 3.0 2.8 2.6 2.4 2.2 2.0 -40 -15 10 35 60 tPHLD tPLHD
3.4 DIFFERENTIAL PROPAGATION DELAY (ns) 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 0.075 0.525 0.975 1.425 1.875 tPHLD tPLHD
3.0 2.8 2.6 2.4 2.2 2.0 1.8 tPHLD tPLHD
85
2.325
0.10
0.38
0.65
0.93
1.20
TEMPERATURE (C)
COMMON-MODE VOLTAGE (V)
DIFFERENTIAL INPUT VOLTAGE (V)
DIFFERENTIAL PULSE SKEW vs. SUPPLY VOLTAGE
MAX9179 toc11
TRANSITION TIME vs. SUPPLY VOLTAGE
MAX9179 toc12
200 DIFFERENTIAL PULSE SKEW (ps) 150 100 50 0 -50 -100 3.0 3.1 3.2 3.3 3.4 3.5
1100 1000 TRANSITION TIME (ps) 900 800 700 600 500
tTLH
tTHL
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TRANSITION TIME vs. TEMPERATURE
MAX9179 toc13
DIFFERENTIAL THRESHOLD VOLTAGE vs. COMMON-MODE VOLTAGE
DIFFERENTIAL THRESHOLD VOLTAGE (mV) 30 20 10 0 -10 -20 -30 -40 0.075 0.525 0.975 1.425 1.875 2.325 VTL VTH
MAX9179 toc14
1200 1100 TRANSITION TIME (ps) 1000 900 800 700 600 500 400 -40 -15 10 35 60 tTLH tTHL
40
85
TEMPERATURE (C)
COMMON-MODE VOLTAGE (V)
6
_______________________________________________________________________________________
Quad LVDS Receiver with Hysteresis
Pin Description
PIN TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 -- QFN 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 EP NAME IN1IN1+ IN2+ IN2IN3IN3+ IN4+ IN4EN OUT4 OUT3 GND VCC OUT2 OUT1 EN Inverting LVDS Input 1 Noninverting LVDS Input 1 Noninverting LVDS Input 2 Inverting LVDS Input 2 Inverting LVDS Input 3 Noninverting LVDS Input 3 Noninverting LVDS Input 4 Inverting LVDS Input 4 Enable Complementary Input. The outputs are active when EN = high and EN = low or open. For all other combinations of EN and EN, the outputs are disabled and in high impedance. LVCMOS/LVTTL Output 4 LVCMOS/LVTTL Output 3 Ground Power-Supply Input. Bypass VCC to GND with 0.1F and 0.001F ceramic capacitors. LVCMOS/LVTTL Output 2 LVCMOS/LVTTL Output 1 Enable Input. The outputs are active when EN = high and EN = low or open. For all other combinations of EN and EN, the outputs are disabled and in high impedance. FUNCTION
MAX9179
Exposed Exposed Pad. Connect to ground. Pad
__________________________________________________________________________
Quad LVDS Receiver with Hysteresis MAX9179
Table 1. Functional Table
ENABLES EN EN INPUTS (IN_+) - (IN_-) +75mV H L or open -75mV Open, undriven short, or undriven terminated All other combinations of enable inputs X OUTPUT OUT_ H L H Z
Input Fail-Safe
The fail-safe feature of the MAX9179 sets the output high when the differential input is: * Open * Undriven and shorted * Undriven and terminated Without a fail-safe circuit, when the input is undriven, noise at the input may switch the output and it may appear to the system that data is being sent. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when a driver output is in high impedance. A shorted input can occur because of a cable failure. When the input is driven with a differential signal of |VID| = 75mV to 1.2V within a voltage range of 0 to 2.4V, the fail-safe circuit is not activated. If the input is open, undriven and shorted, or undriven and terminated, an internal resistor in the fail-safe circuit pulls both inputs above VCC - 0.3V, activating the fail-safe circuit and forcing the output high (Figure 2).
H = High logic level L = Low logic level X = Don't care Z = High impedance
Detailed Description
The LVDS is a signaling method intended for point-topoint communication over a controlled-impedance medium as defined by the ANSI TIA/EIA-644 and IEEE 1596.3 standards. The MAX9179 is a quad LVDS line receiver with built-in hysteresis, intended for high-speed, point-to-point, lowpower applications. The receiver accepts four LVDS input signals and translates them to 3.3V LVCMOS output levels at speeds up to 400Mbps over controlledimpedance media of 100. The hysteresis improves noise immunity and prevents multiple switching due to noise on slow input transitions at the end of a long cable. The receiver is capable of detecting differential signals as low as 75mV and as high as 1.2V within a 0 to 2.4V input voltage range. The 250mV to 450mV differential output of an LVDS driver is nominally centered on a 1.2V offset. This offset, coupled with the receiver's 0 to 2.4V input voltage range, allows an approximate 1V shift in the signal (as seen by the receiver). This allows for a difference in ground references of the transmitter and the receiver, the common-mode effects of coupled noise, or both. The LVDS standards specify an input voltage range of 0 to 2.4V referenced to receiver ground.
Overshoot and Undershoot Voltage Protection
The MAX9179 is designed to protect the enable inputs (EN and EN) against latchup due to transient overshoot and undershoot voltage. If the enable input voltage goes above VCC or below GND by up to 1V, an internal circuit clamps and limits input current to 1.8mA.
Applications Information
Power-Supply Bypassing
Bypass the VCC pin with high-frequency surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to VCC.
Differential Traces
Input trace characteristics affect the performance of the MAX9179. Use controlled-impedance differential traces (100 is typical). To reduce radiated noise and ensure that noise couples as common mode, route the differential input signals within a pair close together. Reduce skew by matching the electrical length of the signal paths making up the differential pair. Excessive skew can result in a degradation of magnetic field cancellation. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Minimize the number of vias to further prevent impedance discontinuities.
Hysteresis
The MAX9179 incorporates hysteresis of 50mV (typ), which rejects noise and prevents false switching during low-slew-rate transitions at the end of a long cable. The receiver typically switches at 25mV above or below VID = 0V (Figure 1). The hysteresis is designed to be symmetrical around VID = 0V for low pulse distortion (see the Typical Operating Characteristics).
8
_______________________________________________________________________________________
Quad LVDS Receiver with Hysteresis
Cables and Connectors
Interconnect for LVDS typically has a controlled differential impedance of 100. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
RC 50 TO 100 CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE RD 330 DISCHARGE RESISTANCE DEVICE UNDER TEST
MAX9179
Cs 150pF
STORAGE CAPACITOR
Termination
The MAX9179 requires external termination resistors. The input termination resistor used on each active channel should match the differential impedance of the transmission line. Place the termination resistor as close to the MAX9179 receiver input as possible. Use 1% surface-mount resistors.
Figure 7. IEC61000-4-2 Test Model
RC 1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE
RD 1.5k DISCHARGE RESISTANCE DEVICE UNDER TEST
Board Layout
Keep the LVDS input and LVCMOS output signals separated from each other to reduce crosstalk; 180 degrees of separation between LVDS inputs and LVCMOS outputs is recommended. Because there are leads on all sides, this separation requires special attention when laying out traces for the QFN package. A four-layer printed circuit board with separate layers for power, ground, LVDS inputs, and single-ended logic signals is recommended. Separate the LVDS signals from the single-ended signals with power and ground planes for best results.
Cs 100pF
STORAGE CAPACITOR
Figure 8. Human Body Test Model
IEC 61000-4-2 Level 4 ESD Protection
The IEC 61000-4-2 standard (Figure 7) specifies ESD tolerance for electronic systems. The IEC61000-4-2 model specifies a 150pF capacitor that is discharged into the device through a 330 resistor. The MAX9179 LVDS inputs are rated for IEC61000-4-2 level 4 (8kV Contact Discharge and 15kV Air-Gap Discharge). The Human Body Model (HBM) (Figure 8) specifies a 100pF capacitor that is discharged into the device through a 1.5k resistor. The IEC 61000-4-2 discharges higher peak current and more energy than the HBM due to the lower series resistance and larger capacitor.
IN1+
Functional Diagram
OUT1 IN1IN2+ OUT2 IN2IN3+ OUT3 IN3IN4+ OUT4 IN4EN EN
Chip Information
TRANSISTOR COUNT: 1173 PROCESS: CMOS
_______________________________________________________________________________________
9
Quad LVDS Receiver with Hysteresis MAX9179
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
10
______________________________________________________________________________________
Quad LVDS Receiver with Hysteresis
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
MAX9179
PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX9179

	To Download MAX9179 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .